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SM5951A seiko npc corporation ? 8-channel dsd editing system signal processor lsi overview the SM5951A is an 8-channel dsd (direct stream digital) editing system signal processor lsi. it takes 4 dsd input signals per channel, mixes them, and then converts the result back into 1-bit dsd data for output. features dsd signal sampling rate: 5.6448mhz (128 44.1khz) and 2.8224mhz (64 44.1khz) supported 8-channel dsd signal mixing 8-channel, 4 dsd signal inputs per channel mixing using arbitrary coef?ients for each input raw signal switching function (auto bypass) automatically switches to raw signal output with no switching noise and no signal degradation when mix- ing is not required, bypassing the mixing processing input/output format normal input/output format where the data changes are synchronized to the bit clock cycle, and manches- ter-type encoding input/output format where the data inverts during the bit clock cycle monitor output: simultaneous 64 44.1khz monitor data output when in 128 44.1khz sampling rate mode microcontroller interface: parallel bi-directional 8-bit/16-bit/32-bit data bus supported master clock: 45.1584mhz (1024 44.1khz) or 56.448mhz (1280 44.1khz) 2 voltage supplies: 3.3v (3.0 to 3.6v) and 2.5v (2.3 to 2.7v) operating temperature range: ? 20 to 70 c package: 160-pin qfp package dimensions (unit: mm) ordering information device package SM5951Af 160-pin qfp 3.35 0.1 0.35 4.0max 28.0 0.1 0.8 0.2 28.0 0.1 31.2 0.4 0.22 to 0.4 0.15 0.11 to 0.23 1.6 0.8 0.65 31.2 0.4 15 15 0 to 10.0
SM5951A seiko npc corporation ? block diagram dsdi1_[3:0] dsdo [8:1] dsdi2_[3:0] dsdi3_[3:0] dsdi4_[3:0] dsdi5_[3:0] dsdi6_[3:0] dsdi7_[3:0] dsdi8_[3:0] exmute bcki seldsdi cs_x rd_x wr_x addr [7:0] data [31:0] sel1280 rst_x dsd i/f selbus [1:0] clk test [8:1] fs clock generator & timing control mixer_blk dsd_sw coef_gen test control bcko dsd64o [8:1] bck64o seldsdo dsd_out (internal clocks & control) mosync conv128to64 (dsd64_i/f) (dsd_i/f) mcu i/f edit req_gen
SM5951A seiko npc corporation ? pinout (top view) 21 vss addr7 22 addr6 23 addr5 24 addr4 25 addr3 26 addr2 27 addr1 28 addr0 29 vss 30 vddh 31 cs_x 32 wr_x 33 rd_x 34 vss 35 vddl 36 test1 37 test2 38 test3 39 test4 40 vss 1 vddl 2 data7 3 data6 4 data5 5 data4 6 vss 7 vddh 8 data3 9 data2 10 data1 11 data0 12 vss 13 vddl 14 rst_x 15 selbus1 16 selbus0 17 sel1280 18 vss 19 clk 20 vddl vss 91 90 89 88 87 86 85 84 83 82 81 100 99 98 97 96 95 94 93 92 dsdi4_3 dsdi4_2 dsdi4_1 dsdi4_0 dsdi3_3 dsdi3_2 dsdi3_1 dsdi3_0 vddh vss dsdi2_3 dsdi2_2 dsdi2_1 dsdi2_0 dsdi1_3 dsdi1_2 dsdi1_1 dsdi1_0 vddl vss 111 110 109 108 107 106 105 104 103 102 101 120 119 118 117 116 115 114 113 112 dsdi8_3 dsdi8_2 dsdi8_1 dsdi8_0 dsdi7_3 dsdi7_2 dsdi7_1 dsdi7_0 vddh vss dsdi6_3 dsdi6_2 dsdi6_1 dsdi6_0 dsdi5_3 dsdi5_2 dsdi5_1 dsdi5_0 vddl vddl test5 test6 test7 test8 vss vddh dsdo1 dsdo2 dsdo3 dsdo4 vss vddl dsdo5 dsdo6 dsdo7 dsdo8 vss vddl bcko 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 vss 62 vddh 63 bck64o 64 vss 65 vddl 66 dsd64o1 67 dsd64o2 68 dsd64o3 69 dsd64o4 70 vss 71 vddl 72 dsd64o5 73 dsd64o6 74 dsd64o7 75 dsd64o8 76 vss 77 vddh 78 seldsdo 79 seldsdi 80 vss 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 data8 data9 data10 data11 vddh vss data12 data13 data14 data15 vddl vss data16 data17 data18 data19 vddh vss data20 data21 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 data22 data23 vddl vss data24 data25 data26 data27 vddh vss data28 data29 data30 data31 mosync fs bcki exmute vddl
SM5951A seiko npc corporation ? pin layout table no. name i/o no. name i/o no. name i/o no. name i/o 1 vddl ? 41 vddl ? 81 vddl ? 121 vddl ? 2 data7 i/o 42 test5 i 82 dsdi1_0 i 122 exmute i 3 data6 i/o 43 test6 i 83 dsdi1_1 i 123 bcki i 4 data5 i/o 44 test7 i 84 dsdi1_2 i 124 fs i 5 data4 i/o 45 test8 i 85 dsdi1_3 i 125 mosync o 6 vss ? 46 vss ? 86 dsdi2_0 i 126 data31 i/o 7 vddh ? 47 vddh ? 87 dsdi2_1 i 127 data30 i/o 8 data3 i/o 48 dsdo1 o 88 dsdi2_2 i 128 data29 i/o 9 data2 i/o 49 dsdo2 o 89 dsdi2_3 i 129 data28 i/o 10 data1 i/o 50 dsdo3 o 90 vss ? 130 vss ? 11 data0 i/o 51 dsdo4 o 91 vddh ? 131 vddh ? 12 vss ? 52 vss ? 92 dsdi3_0 i 132 data27 i/o 13 vddl ? 53 vddl ? 93 dsdi3_1 i 133 data26 i/o 14 rst_x i 54 dsdo5 o 94 dsdi3_2 i 134 data25 i/o 15 selbus1 i 55 dsdo6 o 95 dsdi3_3 i 135 data24 i/o 16 selbus0 i 56 dsdo7 o 96 dsdi4_0 i 136 vss ? 17 sel1280 i 57 dsdo8 o 97 dsdi4_1 i 137 vddl ? 18 vss ? 58 vss ? 98 dsdi4_2 i 138 data23 i/o 19 clk i 59 vddl ? 99 dsdi4_3 i 139 data22 i/o 20 vddl ? 60 bcko o 100 vss ? 140 data21 i/o 21 addr7 i 61 vss ? 101 vddl ? 141 data20 i/o 22 addr6 i 62 vddh ? 102 dsdi5_0 i 142 vss ? 23 addr5 i 63 bck64o o 103 dsdi5_1 i 143 vddh ? 24 addr4 i 64 vss ? 104 dsdi5_2 i 144 data19 i/o 25 addr3 i 65 vddl ? 105 dsdi5_3 i 145 data18 i/o 26 addr2 i 66 dsd64o1 o 106 dsdi6_0 i 146 data17 i/o 27 addr1 i 67 dsd64o2 o 107 dsdi6_1 i 147 data16 i/o 28 addr0 i 68 dsd64o3 o 108 dsdi6_2 i 148 vss ? 29 vss ? 69 dsd64o4 o 109 dsdi6_3 i 149 vddl ? 30 vddh ? 70 vss ? 110 vss ? 150 data15 i/o 31 cs_x i 71 vddl ? 111 vddh ? 151 data14 i/o 32 wr_x i 72 dsd64o5 o 112 dsdi7_0 i 152 data13 i/o 33 rd_x i 73 dsd64o6 o 113 dsdi7_1 i 153 data12 i/o 34 vss ? 74 dsd64o7 o 114 dsdi7_2 i 154 vss ? 35 vddl ? 75 dsd64o8 o 115 dsdi7_3 i 155 vddh ? 36 test1 i 76 vss ? 116 dsdi8_0 i 156 data11 i/o 37 test2 i 77 vddh ? 117 dsdi8_1 i 157 data10 i/o 38 test3 i 78 seldsdo i 118 dsdi8_2 i 158 data9 i/o 39 test4 i 79 seldsdi i 119 dsdi8_3 i 159 data8 i/o 40 vss ? 80 vss ? 120 vss ? 160 vss ?
SM5951A seiko npc corporation ? pin description number of pins name i/o polarity 1 1. attributes: s = schmitt type, pu = with pull-up resistor, pd = with pull-down resistor, ma = output current voltage functional description 1 rst_x i pu, s 3.3v system reset 1fs i ? 3.3v 1fs clock (44.1khz) 1 clk i ? 3.3v master clock 1 sel1280 i pd, s 3.3v select master clock rate [high] : 1280 44.1khz, [low] : 1024 44.1khz 1 seldsdi i pd, s 3.3v select dsd input format [high] : manchester encoding, [low] : normal 1 seldsdo i pd, s 3.3v select dsd output format [high] : manchester encoding, [low] : normal 2 selbus [1:0] i pu, s 3.3v select mcu data bus width [selbus1, selbus0] [low, low] : 8-bit [low, high] : 16-bit [high, (low or high)] : 32-bit 1 cs_x i pu 3.3v mcu i/f : chip select 1 wr_x i pu, s 3.3v mcu i/f : write enable 1 rd_x i pu, s 3.3v mcu i/f : read enable 8 addr [7:0] i pu 3.3v mcu i/f : address bus 32 data [31:0] i/o 3ma 3.3v mcu i/f : data bus 1 bcki i s 3.3v dsd input : bit clock in 4 dsdi1_[3:0] i ? 3.3v dsd input : dsd ch1 data (line0 to line3) 4 dsdi2_[3:0] i ? 3.3v dsd input : dsd ch2 data (line0 to line3) 4 dsdi3_[3:0] i ? 3.3v dsd input : dsd ch3 data (line0 to line3) 4 dsdi4_[3:0] i ? 3.3v dsd input : dsd ch4 data (line0 to line3) 4 dsdi5_[3:0] i ? 3.3v dsd input : dsd ch5 data (line0 to line3) 4 dsdi6_[3:0] i ? 3.3v dsd input : dsd ch6 data (line0 to line3) 4 dsdi7_[3:0] i ? 3.3v dsd input : dsd ch7 data (line0 to line3) 4 dsdi8_[3:0] i ? 3.3v dsd input : dsd ch8 data (line0 to line3) 1 exmute i ? 3.3v dsd input : external mute pattern 1 bcko o 6ma 3.3v dsd output : bit clock out 8 dsdo [8:1] o 3ma 3.3v dsd output : dsd output data (ch1 to ch8) 1 bck64o o 6ma 3.3v dsd 64fs output : bit clock out 8 dsd64o [8:1] o 3ma 3.3v dsd 64fs output : dsd output data (ch1 to ch8) 1 mosync o 3ma 3.3v sync monitor 8 test [8:1] i pd 3.3v iotest_en, scan_en, atpg_en, func_mode etc. 10 vddh ?? 3.3v power supply (i/o) 14 vddl ?? 2.5v power supply (core) 24 vss ?? 0v ground level
SM5951A seiko npc corporation ? specifications absolute maximum ratings v ss = 0v recommended operating conditions v ss = 0v electrical characteristics dc characteristics v ddh = 3.0 to 3.6v, v ddl = 2.3 to 2.7v, v ss = 0v, t opr = ? 20 to 70 c, unless otherwise noted pin summary parameter symbol rating unit supply voltage 1v ddh ? 0.3 to 4.0 v supply voltage 2v ddl ? 0.3 to 3.0 v input voltage (3.3v) v in ?0.3 to v ddh + 0.5 v power dissipation p d 1.3 w storage temperature range t stg ?55 to 125 c parameter symbol rating unit supply voltage 1 v ddh 3.0 to 3.6 v supply voltage 2 v ddl 2.3 to 2.7 v operating temperature t opr ?20 to 70 c parameter pins symbol condition rating unit min typ max current consumption 1 v ddh i ddh all pins no load ?? 8ma current consumption 2 v ddl i ddl all pins no load ?? 550 ma input voltage high-level (*1) v ih v ddh = 3.6v 2.0 ?? v low-level (*1) v il v ddh = 3.0v ?? 0.8 v schmitt trigger voltage positive (*2) v t + 1.1 ? 2.4 v negative (*2) v t ? 0.6 ? 1.8 v hysteresis voltage (*2) v h 0.1 ?? v output voltage high-level (*3) v oh i oh = ? 3ma (type 1), ? 6ma (type 2) v ddh ? 0.4 ?? v low-level (*3) v ol i ol = 3ma (type 1), 6ma (type 2) ?? 0.4 v input leakage current (*1) (*2) i li ? 5 ? 5 a pull-down resistance (*4) r pd v i = v ddh 60 120 288 k ? pull-up resistance (*5) r pu v i = v ss 60 120 288 k ? high-level holding current (*6) i bhh v in = 2.0v , v ddh = 3.0v ??? 20 a low-level holding current (*6) i bhl v in = 0.8v , v ddh = 3.0v ?? 17 a high-level reverse current (*6) i bhho v in = 0.8v , v ddh = 3.6v ? 350 ?? a low-level reverse current (*6) i bhlo v in = 2.0v , v ddh = 3.6v 210 ?? a (*1) input pins and bi-directional pins in input mode (*2) schmitt-characteristic inputs and bi-directional pins in input mode (*3) output pins and bi-directional pins in output mode type 2: bcko, bck64o type 1: all outputs excluding those above (*4) inputs with pull-down resistor (*5) inputs with pull-up resistor (*6) input/outputs with bus hold circuit (data [31:0])
SM5951A seiko npc corporation ? ac characteristics v ddh = 3.0 to 3.6v, v ddl = 2.3 to 2.7v, v ss = 0v, t opr = ? 20 to 70 c unless otherwise noted. when fs = 44.1khz, the fs and bcki clock inputs have the following frequency division relationship to the master clock input on clk. when clk = 1024fs: (fs) cycle = 1024 clk cycles (bcki) cycle [128fs mode] = 8 clk cycles (128fs) (bcki) cycle [64fs mode] = 16 clk cycles (64fs) when clk = 1280fs: (fs) cycle = 1280 clk cycles (bcki) cycle [128fs mode] = 10 clk cycles (128fs) (bcki) cycle [64fs mode] = 20 clk cycles (64fs) system clock input clk pin 1fs clock input fs pin (44.1khz) parameter symbol rating unit min typ max high-level pulsewidth t mcwh 7 11.07 (1024fs) 8.86 (1280fs) ? ns low-level pulsewidth t mcwl 7 11.07 (1024fs) 8.86 (1280fs) ? ns pulse cycle t mcy 16 22.14 (1024fs) 17.72 (1280fs) ? ns rise/fall time t r , t f ?? 2ns parameter symbol rating unit min typ max high-level pulsewidth t fscwh ? 11.34 ? s low-level pulsewidth t fscwl ? 11.34 ? s pulse cycle t fscy ? 22.68 ? s rise/fall time t fsr , t fsf ?? 10 ns clk t mcy t mcwh t mcwl t r t f v ddh 90% v ddh 50% v ddh 10% fs t fscy t fscwh t fscwl t fsr t fsf v ddh 90% v ddh 50% v ddh 10%
SM5951A seiko npc corporation ? dsd input/output fs, bcki, dsdi , exmute, bcko, bck64o, dsdo , dsd64o pins 1. normal mode rating (input data setup time is referenced to the bcki rising edge) 2. manchester-type mode rating (input data setup time is referenced to the bcki falling edge) 3. the delay in the state of internal synchronization relative to the fs input edge parameter symbol rating unit min typ max dsd bit clock pulsewidth t dscw 80 177.16 (1/64fs) 88.58 (1/128fs) ? ns dsd bit clock pulse cycle t dscy ? 354.31 ( 1/64fs) 177.16 (1/128fs) ? ns dsd 64fs bit clock output pulsewidth t ds64cw ? 177.16 ? ns dsd 64fs clock output pulse cycle t ds64cy ? 354.31 ? ns dsd data input setup time 1 t dss 35 ?? ns dsd data input hold time 1 t dsh 35 ?? ns dsd data input setup time 2 t dsms ?? 18 ns dsd data input hold time 2 t dsmh 0 ?? ns dsd data output delay time t dsod 0 ? 10 ns dsd bit clock output delay time 3 t dscdly 0 ? 88 ns bcki t dscy t dss t dscw t dsh t dscw t dsmh t dsms bcko t dscy t dscw t dscw t dsod fs t dscdly bck64o t ds64cw t ds64cw t dscdly t ds64cy dsdi 2 dsdi exmute 1 dsd64o 2 dsd64o 1 dsdo 1 dsdo 2 t dsod t dsod t dsod t dsod t dsod
SM5951A seiko npc corporation ? mcu interface addr [7:0], cs_x, rd_x, wr_x, data [31:0] pins initialization rst_x pin parameter symbol rating unit min typ max access cycle time t accy 150 ?? ns addr, cs_x setup time t ads 10 ?? ns addr, cs_x hold time t adh 10 ?? ns rd_x pulsewidth t rlw 100 ?? ns wr_x pulsewidth t wlw 100 ?? ns read data output delay time t rdzd 0 ? 20 ns read data de?ed delay time t rdtd 0 ? 60 ns read data output ?ating delay time t rdfd 0 ? 10 ns write data input setup time t wds 20 ?? ns write data input hold time t wdh 10 ?? ns parameter symbol rating unit min typ max initialization time t intm 6 t mcy ?? ns addr [7:0] t accy t ads t rlw t adh t ads t wlw t adh t rdzd t rdtd t rdfd t wdh t wds cs_x rd_x wr_x data (out) data (in) hi-z hi-z hi-z v ddh t intm rst_x t intm 3.0v
SM5951A seiko npc corporation ?0 functional description data input/output format dsd input format the dsd input format can be set to one of 2 types by the state of seldsdi. (1) normal mode (seldsdi = low) dsd input data is read in close to the rising edge of the bit clock bcki. note that even if the input is phase modulated, the data is still read in close to the rising edge of bcki if the data is de?ed. (2) manchester-type input (seldsdi = high) dsd input data is read in during the low-level pulse of the bit clock bcki. note. dsdi***: dsdi1_[3:0], dsdi2_[3:0], dsdi3_[3:0], dsdi4_[3:0], dsdi5_[3:0], dsdi6_[3:0], dsdi7_[3:0], dsdi8_[3:0] pins note. when an external mute pattern is input on exmute pin, data is read in normal mode format only, regardless of the state of seldsdi. dsdi*** d1 d2 d1 d1 d2 d2 bcki (1/64fs or 1/128fs) dsdi*** d1 d2 bcki (1/64fs or 1/128fs) d1 d2
SM5951A seiko npc corporation ?1 dsd output format the dsd output format can be set to one of 2 types by the state of seldsdo. (1) normal mode (seldsdo = low) dsd output data transitions occur on the falling edge of the bit clock bcko. (2) manchester-type output (seldsdo = high) dsd output data transitions occur on the falling edge of the bit clock bcko and then inverts on the rising edge of the bit clock bcko. note. dsdo*: dsdo [8:1] pins, dsd64o*: dsd64o [8:1] pins mcu interface bus access control the internal mode and coef?ients can be set using either 8/16/32-bit data bus, facilitating easy connection to various kinds of mcu bus. the data bus control pins are active low. when the chip select (cs_x) is active, read/write control inputs are valid. when write control (wr_x) is active, data is written in on the rising edge. data is read out when the read control (rd_x) is active. note. data [31:0] pins have an additional bus hold circuit which holds the previous data even when the pin is in a high-impedan ce ( " hi-z " ) state. dsdo* d1 d2 bcko (1/64fs or 1/128fs) bck64o dsd64o* dsdo* d1 d2 bcko (1/64fs or 1/128fs) d1 d2 bck64o dsd64o* addr [7:0] cs_x rd_x wr_x data [31:0] (out) data [31:0] (in) hi-z hi-z hi-z data (out) data (in)
SM5951A seiko npc corporation ?2 data bus width selection the width of the data bus for data access can be set to one of 3 types by the state of the selbus [1:0] pins. (1) 32-bit bus: selbus [1:0] = (1, ) (2) 16-bit bus: selbus [1:0] = (0, 1) (3) 8-bit bus: selbus [1:0] = (0, 0) internally, parameter settings and data are handled in 32-bit units, while the memory area addresses are han- dled in 8-bit units. for 8-bit and 16-bit access bus widths, the 2 least signi?ant address bits (addr [1:0]) are used to determine which internal data bits are accessed as shown in the following table. note. " " in the address column are don't care bits. note. addr [1:0] pins are not used . micro controller (32bit data bus) (chip_enable) (data_bus [31, 24]) (data_bus [23, 16]) (data_bus [15, 8]) (data_bus [7, 0]) (address) cs_x wr_x rd_x data [31, 24] data [23, 16] data [15, 8] data [7, 0] (write_enable) (read_enable) (vddh or vss) (vddh or vss) addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0 selbus1 selbus0 vddh vddh or vss SM5951A note. addr0, data [31:16] pins are not used . micro controller (16bit data bus) (chip_enable) (data_bus [15, 8]) (data_bus [7, 0]) (address) cs_x wr_x rd_x data [31, 24] data [23, 16] data [15, 8] data [7, 0] (write_enable) (read_enable) (vddh or vss) addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0 selbus1 selbus0 vss vddh SM5951A (no connect) (no connect) note. data [31:8] pins are not used . micro controller (8bit data bus) (chip_enable) (data_bus [7, 0]) (address) cs_x wr_x rd_x data [31, 24] data [23, 16] data [15, 8] data [7, 0] (write_enable) (read_enable) addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0 selbus1 selbus0 vss vss SM5951A (no connect) (no connect) (no connect) internal data bit 32-bit access 16-bit access 8-bit access addr [1:0] data pin addr [1:0] data pin addr [1:0] data pin 7-0 bit ( , ) data [7:0] (0, ) data [7:0] (0, 0) data [7:0] 15-8 bit ( , ) data [15:8] (0, ) data [15:8] (0, 1) data [7:0] 23-16 bit ( , ) data [23:16] (1, ) data [7:0] (1, 0) data [7:0] 31-24 bit ( , ) data [31:24] (1, ) data [15:8] (1, 1) data [7:0]
SM5951A seiko npc corporation ?3 address mapping address read/ write initial value data bit 31 24 23 16 15 8 7 0 03h-00h r/w 8bh control [7] = offpat [6] = dconven [5:4] = dith [1:0] [3] = dithen [2] = mutesel [1] = dsd128 [0] = sreset 07h-04h r ? switching status [31:28] = stat_ch8 [27:24] = stat_ch7 [23:20] = stat_ch6 [19:16] = stat_ch5 [15:12] = stat_ch4 [11:8] = stat_ch3 [7:4] = stat_ch2 [3:0] = stat_ch1 0bh-08h r/w 076543h pattern match no. [23:20] = (reserved) [19:16] = match8 [15:12] = match7 [11:8] = match6 [7:4] = match5 [3:0] = match4 0fh-0ch r ? matching status [31:28] = match_ch8 [27:24] = match_ch7 [23:20] = match_ch6 [19:16] = match_ch5 [15:12] = match_ch4 [11:8] = match_ch3 [7:4] = match_ch2 [3:0] = match_ch1 13h-10h r/w 152b6bh delay offset [23:21] = (reserved) [20:16] = dly_down [15] = (reserved) [14:8] = dly_64 [7] = (reserved) [6:0] = dly_128 7fh-14h ?? 83h-80h r/w 000000h ch1 coef?ient [23:0] = ch1coef1 87h-84h r/w 000000h [23:0] = ch1coef2 8bh-88h r/w 000000h [23:0] = ch1coef3 8fh-8ch r/w 000000h [23:0] = ch1coef4 93h-90h r/w 000000h ch2 coef?ient [23:0] = ch2coef1 97h-94h r/w 000000h [23:0] = ch2coef2 9bh-98h r/w 000000h [23:0] = ch2coef3 9fh-9ch r/w 000000h [23:0] = ch2coef4 a3h-a0h r/w 000000h ch3 coef?ient [23:0] = ch3coef1 a7h-a4h r/w 000000h [23:0] = ch3coef2 abh-a8h r/w 000000h [23:0] = ch3coef3 afh-ach r/w 000000h [23:0] = ch3coef4 b3h-b0h r/w 000000h ch4 coef?ient [23:0] = ch4coef1 b7h-b4h r/w 000000h [23:0] = ch4coef2 bbh-b8h r/w 000000h [23:0] = ch4coef3 bfh-bch r/w 000000h [23:0] = ch4coef4 c3h-c0h r/w 000000h ch5 coef?ient [23:0] = ch5coef1 c7h-c4h r/w 000000h [23:0] = ch5coef2 cbh-c8h r/w 000000h [23:0] = ch5coef3 cfh-cch r/w 000000h [23:0] = ch5coef4 d3h-d0h r/w 000000h ch6 coef?ient [23:0] = ch6coef1 d7h-d4h r/w 000000h [23:0] = ch6coef2 dbh-d8h r/w 000000h [23:0] = ch6coef3 dfh-dch r/w 000000h [23:0] = ch6coef4 e3h-e0h r/w 000000h ch7 coef?ient [23:0] = ch7coef1 e7h-e4h r/w 000000h [23:0] = ch7coef2 ebh-e8h r/w 000000h [23:0] = ch7coef3 efh-ech r/w 000000h [23:0] = ch7coef4 f3h-f0h r/w 000000h ch8 coef?ient [23:0] = ch8coef1 f7h-f4h r/w 000000h [23:0] = ch8coef2 fbh-f8h r/w 000000h [23:0] = ch8coef3 ffh-fch r/w 000000h [23:0] = ch8coef4
SM5951A seiko npc corporation ?4 control register the ic operating state is set by the control register. bit 0: sreset (default = 1) 1: state retention 0: reset and resync when set to ?? it resets the internal computational block data and resynchronizes timing. when reset and resynchronization ?ishes, it is automatically set to 1 and the device is in computation mode. this bit is write-only, and reading this bit has no meaning. bit 1: dsd128 (default = 1) 1: 128fs 0: 64fs selects the dsd input/output sampling frequency (fs = 44.1khz). however, the dsd64o output always has 64fs dsd sampling rate, regardless of this bit setting. bit 2: mutesel (default = 0) 1: external input 0: internal selects the mute pattern used when mixing. the internally generated pattern is [10010110], while the external input mute pattern is entered on the exmute pin. bit 3: dithen (default = 1) 1: dither on 0: dither off this applies to the dither when converting the 128fs dsd signal (dsdo*) to the 64fs dsd signal (dsd64o*). selects dither on/off. bit [5, 4]: dith (default = [0, 0]) [1, 1]: 1/256 [1, 0]: 1/128 [0, 1]: 1/64 [0, 0]: 1/32 this applies to the dither when converting the 128fs dsd signal (dsdo*) to the 64fs dsd signal (dsd64o*). sets the dither level applied. bit 6: dconven (default = 0) 1: on 0: off when 128fs dsd signal sampling frequency is selected, this bit selects whether down conversion to 64fs dsd signal (dsd64o*) is performed or not. active only when dsd128 (bit 1) is set to ?? bit 7: offpat (default = 1) 1: ?6h?mute pattern 0: ???ed when 128fs dsd signal is not selected and down conversion is off, this bit selects the 64fs dsd signal (dsd64o*) output pattern. when 128fs dsd signal is selected (dsd128 is set to ?? and down conversion is on (dconven is set to ??, this bit is inactive and the down converted 64fs dsd signal is output on dsd64o*. note. dsdo*: dsdo [8:1] pins, dsd64o*: dsd64o [8:1] pins address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00h offpat dconven dith1 dith0 dithen mutesel dsd128 sreset
SM5951A seiko npc corporation ?5 switching status the following addresses are used to monitor the switching status. this area of memory is read-only. the value of each address indicates the following operating status. 0 : input dsd data is being passed directly to the output 1 : switching from direct output (state 0) to internal computation output 4 : internal dsm computation result signal is being output 7 to 9 : switching from state 4 to state 0 other : not used setting the number of pattern matching bits the following addresses are used to set the minimum number of matching bits in each stage of the dsd input signal switching process during mixing. match8 [3:0] (number of matching bits in 1st stage) ? 1, (default = 7) match7 [3:0] (number of matching bits in 2nd stage) ? 1, (default = 6) match6 [3:0] (number of matching bits in 3rd stage) ? 1, (default = 5) match5 [3:0] (number of matching bits in 4th stage) ? 1, (default = 4) match4 [3:0] (number of matching bits in 5th stage) ? 1, (default = 3) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 04h stat_ch2 [3:0] stat_ch1 [3:0] address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 05h stat_ch4 [3:0] stat_ch3 [3:0] address bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 06h stat_ch6 [3:0] stat_ch5 [3:0] address bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 07h stat_ch8 [3:0] stat_ch7 [3:0] address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 08h match5 [3:0] match4 [3:0] address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 09h match7 [3:0] match6 [3:0] address bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0ah (reserved) match8 [3:0] address bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0bh (reserved) (reserved)
SM5951A seiko npc corporation ?6 reading the number of pattern matching bits the following addresses are used to read out the number of matching bits in each stage of the dsd input signal switching process during mixing. match_ch1 [3:0] (number of channel 1 matching bits) ? 1 match_ch2 [3:0] (number of channel 2 matching bits) ? 1 match_ch3 [3:0] (number of channel 3 matching bits) ? 1 match_ch4 [3:0] (number of channel 4 matching bits) ? 1 match_ch5 [3:0] (number of channel 5 matching bits) ? 1 match_ch6 [3:0] (number of channel 6 matching bits) ? 1 match_ch7 [3:0] (number of channel 7 matching bits) ? 1 match_ch8 [3:0] (number of channel 8 matching bits) ? 1 output delay correction these addresses are used to set the mixing delay correction for the dsd input. the setting adjusts the time from dsd input to dsd output by an internal delay in units of the dsd rate. the actual adjustment is the value written to memory + 1. dly_128 [6:0] (default = 107) : delay value when sample rate is 128fs dly_64 [6:0] (default = 43) : delay value when sample rate is 64fs dly_down [4:0] (default = 21) : delay value when down sampling from dsdo (128fs) to dsd64o (64fs) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0ch match_ch2 [3:0] match_ch1 [3:0] address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 0dh match_ch4 [3:0] match_ch3 [3:0] address bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 0eh match_ch6 [3:0] match_ch5 [3:0] address bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 0fh match_ch8 [3:0] match_ch7 [3:0] address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 10h (reserved) dly_128 [6:0] address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 11h (reserved) dly_64 [6:0] address bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 12h (reserved) dly_down [4:0] address bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 13h (reserved)
SM5951A seiko npc corporation ?7 coef?ients the address space 80h to ffh contains 32 coef?ient registers, comprising independent mixing coef?ients for the 4 dsd inputs for each of the 8 channels. chncoefm [23:0]: n-channel m-input coef?ient (default = 0) coef?ients are represented in linear, 2s-complement, 24-bit format. minus coef?ients have inverted polarity. gain setting and positive/inverse (minus) polarity are represented as follows: positive: 0db (input level 1.0) = 080000h positive maximum: 7fffffh ( + 24db) inverse : 0db (input level ? 1.0) = f80000h inverse maximum : 800000h ( + 24db) note 1: when the gain setting is + 12db, ? modulator saturation during requantization may cause noise to increase considerably. note 2: coef?ients are read in during an interval close to the rising edge of fs (44.1khz). if coef?ient data write timing starts and/or ends in this interval, computation using written-in data can be uncertain for an interval of 1fs until its certainly renewed at the next fetch timing. hence, writing coef?ient data during this interval should be avoided. coefficient register internal computation coefficient coff (n) coff (n) coff (n + 1) coff (n + 1) t = 1/44.1khz recommended coefficient write timing fs 0.1 s 1.18 s read interval (max)
SM5951A seiko npc corporation ?8 mixing input signal mixing this stage mixes the 4 dsd input signals on each channel. each dsd signal is multiplied by its corresponding coef?ient and then added, and the result is converted back into a 1-bit dsd signal by a ? modulator. the dsd input signal represents + 1.0 when high and ? 1.0 when low. if the mute pattern is selected during mixing, the muting coef?ients are also multiplied and added. coef?ient interpolation and output switching the mixing coef?ients are read in every 1fs cycle, and linearly interpolated for each dsd sample. the mute pattern coef?ients are automatically calculated from the other input coef?ients. if one of the 4 dsd input coef?ients is 1.0 or ? 1.0 and the other 3 input coef?ients are all 0, the correspond- ing dsd input is switched directly to the output through a delay circuit, avoiding any signal degradation caused by the ? modulator. if all 4 coef?ients are 0, the mute pattern path is switched and output through the delay circuit. the dsm ( ? modulator) bypass condition is automatically calculated from the individual coef?ients. the bypass switching occurs when the dsm output matches the delayed output pattern in order to minimize noise generation. (chncoef1) dsdin_0 dsdin_1 (chncoef2) dsdin_2 (chncoef3) dsdin_3 (chncoef4) (mute_coef) (mute pattern) delay dsm switch (dsd_outn) (sw control)
SM5951A seiko npc corporation ?9 128fs 64fs down conversion the 128fs dsd output is passed through a 51-tap fir ?ter that cuts high-frequency noise, then it is down- sampled to 64fs. the signal is reconverted by a ? modulator into a 64fs dsd signal for output on dso64on. synchronization input clock synchronization the internal computation and interface operation timing are based on the internal word clocks word boundary signal (enfs), regardless of the bcki input state, so that they are always synchronized. they are synchronized on the ?st rising edge of the word clock input on fs after initialization by pin rst_x rising edge or writing to the sreset bit (ad = 00h) of the control register. also, bcki is synchronized on the ?st falling edge after initialization. the internal synchronization status can be monitored on pin mosync. the bcki and fs synchronization status are checked at the beginning of the word clock cycle. if synchronization is maintained for 2 consecutive word clock cycles, mosync goes high, with the same timing as fs, to indicate successful synchronization. mosync immediately goes low whenever bcki or fs lose synchronization, indicating resynchronization is required. (dsd_outn) (dsdon) fir filter (dsd64on) dsm (bcki sync) rst_x bcki ... fs (async) (sync) (clock out) (clr) bcko, bck64o (data clear) mosync (async) (sync)
SM5951A seiko npc corporation ?0 monitoring word clock synchronization the fs input rising edge synchronization status is always monitored internally. it is monitored in a window ? 2 to + 1 master clock cycles wide relative to the current synchronization timing. if the fs input rising edge occurs outside the window, an fs synchronization error occurs and resynchronization is required. monitoring input bit clock synchronization the bcki input falling edge synchronization status is always monitored internally. it is monitored in a window ? 2 to + 1 master clock cycles wide relative to the current synchronization timing. if the bcki input falling edge occurs outside the window, a bcki synchronization error occurs and resynchronization is required. word boundary timing bit boundary timing fs clk (clocked fs) (enfs) ( internal fs timing watch window ) (fs sync error) (fs sync ok) (fs sync error) (internal fs start timing) bcki clk (clocked bcki) (internal bit boundary) ( internal bit timing watch window ) (bcki sync error) (bcki sync ok) (bcki sync error) (internal bit count start timing )
SM5951A seiko npc corporation ?1 dsd signal delay information and adjustment the dsd signal internal process ?w is shown in the following diagram. each stage of the process increases the data delay, and the delay is adjusted internally so that the delay is approximately 1fs cycle. input-stage delay (i/o buffer) the input processing delay due to dsd input format status and the bcki/fs phase relationship is approxi- mately 0.5 to 1.5 samples in length. (1) normal mode timing example dsdin_m i/o buff mix (1) dsm (16) sw (1) fir filter (26) dsm (32) delay down dsdon dsd64on delay = 58 (128fs sample) delay = 18 (dsd sample) delay 128 or delay 64 bcki (max) (clocked) nn + 2 n + 1 n ? 1 n + 1 n bcki (max) bcki (min) dsdi (min) delay (max) delay (min) bcki (min) (clocked) dsd buff1 (max) (input block) dsd buff1 (min) (input block) n ? 1 n + 1 n n ? 2 dsd buff2 [ch8:ch1] (input block) (enfs) clk (1024fs) bcko dsd input (edit block) ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch1 ch2 ch3 ch4 ch5 ch6 ch7 coef input (edit block) n ? 1 n n + 1 dsdi (max) ch8 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 n + 1 n + 1
SM5951A seiko npc corporation ?2 (2) manchester-type input mode timing example internal computation delay the mixing process internal data delay is determined by the dsd sampling frequency and is 18 samples in length. the down-sampled 64fs output has an additional delay of 58 samples in length at 128fs rate. delay adjustment the internal delay immediately before output can be adjusted in units of the sample rate. the delay adjustment can be set in the following internal registers. (1) dly_128 [6:0] (address = 10h) dsdon delay in 128fs mode (2) dly_64 [6:0] (address = 11h) dsdon delay in 64fs mode (3) dly_down [4:0] (address = 12h) dsdon dsd64on delay bcki (max) (clocked) nn + 2 n + 1 n ? 1 n + 1 n bcki (max) bcki (min) dsdi (min) delay (max) delay (min) bcki (min) (clocked) dsd buff1 (max) (input block) dsd buff1 (min) (input block) n ? 1 n + 1 n n ? 2 dsd buff2 [ch8:ch1] (input block) (enfs) clk (1024fs) bcko dsd input (edit block) ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch1 ch2 ch3 ch4 ch5 ch6 ch7 coef input (edit block) n ? 1 n n + 1 dsdi (max) ch8 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 n + 1 n + 1 n + 1 n + 1
SM5951A seiko npc corporation ?3 initialization after power is applied, rst_x must be held low for the rated time to initialize the device. during initialization, the data bus is in input mode. the output pins have the following state. dsd data outputs: low bcko, bck64o: low mosync : low when rst_x goes high, the synchronization adjustment takes place and internal operation commences. when the initialization is performed by software reset in sreset (address = 0), the coef?ient registers (addresses = 80h to ffh) are cleared, but the internal state registers (addresses = 00h to 7fh) maintain their current setting.
SM5951A seiko npc corporation ?4 nc0319ce 2006.04 please pay your attention to the following points at time of using the products shown in this document. the products shown in this document (hereinafter ?roducts? are not intended to be used for the apparatus that exerts harmful in?ence on human lives due to the defects, failure or malfunction of the products. customers are requested to obtain prior written agreeme nt for such use from seiko npc corporation (hereinafter ?pc?. customers shall be solely responsible for, and indemnify and hold npc free and harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. npc reserves the right to change the speci?ations of the products in order to improve the characteristic or reliability thereof. npc makes no claim o r warranty that the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties. therefore, npc shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in t his document. any descriptions including applications, circuits, and the parameters of the products in this document are for reference to use the products, and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further te sting or modi?ation. customers are requested not to export or re-export, directly or indirectly, the products to any country or any ent ity not in compliance with or in violation of the national export administration laws, treaties, orders and regulations. customers are req uested appropriately take steps to obtain required permissions or approvals from appropriate government agencies. seiko npc corporation 15-6, nihombashi-kabutocho, chuo-ku, tokyo 103-0026, japan telephone: +81-3-6667-6601 facsimile: +81-3-6667-6611 http://www.npc.co.jp/ email: sales @ npc.co.jp

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